1. Field of the Invention
The present invention relates to a method of testing apparatus which includes a master logic unit and a slave logic unit.
2. Description of the Related Art
When an apparatus which includes a master logic unit and slave logic units, each of which is connected by a bus, is manufactured, a test for verifying that operation of the slave logic units is operated by the master logic unit correctly is needed. Such a technique of the testing is disclosed in Japanese Patent Laid-Open 2002-140311.
The test is performed by checking a response which is output from a DUT (Device Under Test). The response is output from the DUT in response to a test pattern from a virtual master logic unit. The DUT is one of the slave logic units to be tested. An example of the conventional testing is described by referring to FIG. 6 and FIG. 7.
FIG. 6 is a block diagram showing a structure of a conventional testing apparatus. The structure includes a test pattern storing unit 101, a virtual master logic unit 102, a transfer checker 103, a DUT 104, a virtual slave logic unit 105, a default slave logic unit 106, and an on-chip bus 107. A test pattern which is stored in the test pattern storing unit 101 is written by task texts of Verilog-HDL. Verilog-HDL is a kind of programming language. If the on-chip bus 107 is used for AMBA-AHB (Advanced Microcontroller Bus Architecture (registered trademark of ARM Ltd)—Advanced High-performance Bus), the test pattern is described by a form which is shown in FIG. 7. The test pattern which is shown in FIG. 7 is called a transfer task.
The form of the transfer task includes a type of task (1) which shows a read mode or a write mode and parameters (2) to (8). The parameter includes a type of transferring (2), a type of bursting (3), a transferring bit size (4), an address of the transferring direction (5), an expected read data which is output from the slave logic unit (6), an expected response (OKAY shows a success of a bus transferring, ERROR shows a failure of the bus transferring, and RETRY shows a retry of the bus transferring) (7), and an expected waiting time (8).
The transfer task includes the parameter of nwait for setting the waiting time as shown in FIG. 7. The transfer checker 103 checks the on-chip bus 107 and judges whether the DUT is operated correctly or not, by comparing the expected value which is transferred from the virtual master unit 102 and response which is transferred from the DUT 104.
The waiting time which is included in the expected value is varied for respective types of the slaves or respective types of transferring.
The default slave logic unit 106 returns a response, when any of the other slaves do not return any response.
Next, an operation of the testing is described. First, the virtual master logic unit 102 receives the transfer task from the test pattern storing unit 101, and outputs the transfer task to the on-chip bus 107. This operation is called as a bus transfer. The expected value which includes read data and the waiting time in the transfer task is output from the virtual master logic unit 102 to the transfer checker 103.
Then, the slave logic unit (DUT) 104 which is accessed by the transfer task returns the response.
Then, the transfer checker 103 checks the on-chip bus 107, and compares the expected value in the transfer task with the response from the DUT 104.
After receiving the response from the DUT 104, the virtual master logic unit 102 transfers a next transfer task to the on-chip bus 107.
Next, the test pattern is described below. Each of the slave logic units must respond correctly, even if the responding is performed after the other slave logic unit is responded with predetermined waiting time n (n=1, 2, . . . , ). For checking this responding operation, the virtual slave logic unit 105 has been used. The virtual slave logic unit 105 includes a table which has a relationship between the address which is accessed by the virtual master logic unit 102 and the waiting time as shown in FIG. 8. The waiting time is decided based on the table. For example, when the virtual master logic unit 102 accesses the address range of 000-099 of the table, the waiting time is “0” clock cycles and the virtual slave logic unit 105 responds without waiting as shown in FIG. 9. Alternatively, when the virtual master logic unit 102 accesses the address range of 100-199 of the table, the waiting time is “1” clock cycles and the virtual slave logic unit 105 responds after “1” clock cycles waiting. When the virtual master logic unit 102 accesses the address range of 500-599 of the table, the waiting time is “5” clock cycles and the virtual slave logic unit 105 responds after “5” clock cycles waiting.
An example of the test pattern is described in FIG. 10. In this example, the virtual master logic unit 102 outputs a bus transfer which requires a responding with “0” waiting time to the virtual slave logic unit 105. Then, the virtual master logic unit 102 outputs a bus transfer which requires a responding with “1” waiting time to the DUT. Then, the virtual master logic unit 102 outputs a bus transfer which requires a responding with “2” waiting time to the virtual slave logic unit 105. Then, the virtual master logic unit 102 outputs a bus transfer which requires a responding with “3” waiting time to the DUT.
For checking the operation of the DUT after accessing at the various waiting times, the test pattern which includes the various waiting times is required. However, in the conventional method, the number of the patterns is dependent on the number of the waiting times “n”. That is, if a lot of waiting times “n” such as ten thousands or more is needed, a lot of test patterns are needed. Therefore, if a lot of waiting times are needed, the checking for all waiting times is difficult.